SYNOPSYS: APPLICATION ENGINEER
Eligibility:
- BE or ME/MS with 0-1+ years of experience in logic design and implementation using FPGAs.
- Excellent communication and interpersonal skills, professional attitude and desire to succeed.
- Exposure to Xilinx synthesis software is a plus.
Scripting knowledge is desirable. - Understanding of Verification concepts and writing test benches
- Hands on knowledge in Verilog and/or VHDL.
- Proven problem solving skills.
- Knowledge in Synthesis, back end flow, FPGA architecture and implementing designs in hardware.